Synchronized control system for slow moving equipment



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April 29, 1969 From Ampl.

Timing Pulse Gen.

D. S. NOBLE SYNCHRONIZED CONTROL SYSTEM FOR SLOW MOVING EQUIPMENT FiledFeb. 19, 1968 2?? Shot MV One Shot MV- Sheet Fig. 2.

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April 29, 1969 D. S. NOBLE SYNCHRONIZED CONTROL SYSTEM FOR SLOW MOVINGEQUIPMENT Ap 29, 9 D. s. NOBLE 3, ,744

I SYNOHRONIZED CONTROL SYSTEM FOR SLOW MOVING EQUIPMENT Filed Feb. 19,1968 Sheet 4 of 4 I E 1 E Flg 6 United States Patent US. Cl. 307-40Claims ABSTRACT OF THE DISCLOSURE A cyclic electronic circuit, such as abinary counter, is operated in synchronism with a cylic high speedstorage device, such as a magnetic drum, sonic delay line or shiftregisters operated in a cyclic manner, to generate different strobepulses for each and any or all of its states corresponding to anydesired points in the cycle of the storage. The cyclic circuit issynchronized with the storage by means of a reference or timing pulsechannel in or coupled to the storage unit in such a manner that pulsesare added to the timing pulses or timing pulses are subtracted from theseries of timing pulses in accordance with a slow speed pulse generatorcoupled to the slow moving physical equipment. The movement of the slowmoving physical equipment will thus cause a precession of the cycliccircuit and its associated strobe pulses with respect to the storageunit.

This invention relates to a control system and particularly to anelectronic control system that synchronizes electronic circuitry withslow moving equipment such as conveyor belts and the like.

In electronic control systems for industrial uses, the problemfrequently arises in which it is necessary to synchronize electroniccircuitry with slow moving equipment. Conventionally, this has requireda slow moving storage such as a magnetic tape which is mechanicallysynchronized or a shift register circuit configuration that can beactuated electronically in step with the belt, for example. It has beenfound that the slow moving storage systems are cumbersome, expensive andrather complicated and, accordingly, have proven to be less thanreliable. Generally, these conventional systems also re quire a separatememory track or tape for each actuator to be energized in the system. Itshould be quite obvious that an electronic control system that isphysically simpler, cheaper, smaller, or combinations of these featureswould be a significant advancement of the art.

It is therefore an object of this invention to provide an improvedcontrol system.

It is another object of the present invention to provide a simpler,cheaper and smaller electronic control system.

It is still another object of the invention to provide a control systemfor industrial purposes that does not use a slow moving storage.

It is yet another object of the present invention to provide a controlsystem that does not require a separate memory track or tape for eachactuator to be energized in the system.

It is a further object of the invention to provide a more reliableelectronic control system that utilizes a high speed storage circuitcyclically operated and synchronized to a slow speed mechanical device.

Briefly, the synchronized control system in accordance with theprinciples of the invention includes a cyclic storage unit, a cyclicelectronic circuit that generates different strobe pulses for any of itsstates corresponding to any desired points in the cycle of the storage,a slow speed pulse generator coupled to a slow moving physical unit,

3,4 4 l, Patented Apr. 29, 1 969 ice and timing pulse circuitry coupledto the storage unit, to the cyclic electronic circuit and to the slowspeed pulse generator to cause a precession of the cyclic circuit andits associated strobe pulses with respect to the storage unit by theaddition or subtraction of a timing pulse to the cyclic circuit.

The invention and specific embodiments thereof will be describedhereinafter by way of example and with reference to the accompanyingdrawings wherein like reference numerals refer to like elements or partsand in which:

FIG. 1 is a schematic block diagram of the synchronized control systemin accordance with the principles of the invention operating in anaddition mode;

FIG. 2 is a schematic block diagram of the timing pulse generatorportion of the system of FIG. 1;

FIG. 3 is a schematic diagram of waveforms of voltage as a function oftime for explaining the operation of the timing pulse generator of FIG.2;

FIG. 4 is a schematic block diagram of a single pulse forming circuitportion of the system of FIG. 1;

FIG. 5 illustrates waveforms of voltage as a function of time forexplaining the operation of the single pulse forming circuit of FIG. 4in the addition mode; and

FIG. 6 is a schematic diagram of waveforms of voltage as a function oftime for explaining the operation of the system of FIG. 1.

Referring first to FIG. 1, the synchronized control system in accordancewith the principles of the invention includes a relatively high speedcyclic storage device such as a magnetic drum 11, or a sonic delay line,shift register or other suitable storage arrangements operating in acyclic manner. The magnetic drum 11 as shown may have multiple memorytracks, each having a plurality of stored information segmentspre-recorded thereon which information is received from each such trackby conventional means such as read heads 13 and 15, in this casemagnetically coupled to separate tracks on the magnetic drum 11.

The system according to the invention also includes clock or timingcircuitry which may be independent of the storage means or, as shown inFIG. 1, the magnetic drum 11, for example, may include a clock or timingtrack that is read by a timing read head 17. As an alternative, thetiming circuitry may, as noted, be a separate master oscillator andsuitable pulse forming circuits as well known in the art and, therefore,not shown. The timing information as read by the read head 17 may beamplified by an amplifier 19 before being coupled to the input 21 of atiming pulse generator 23 which will be described in more detail later.

The timing pulse generator 23 includes a first output terminal 25 and asecond output terminal 27 providing, respectively, a first timing signaland a second timing signal a The timing signals are synchronized withthe timing information received at the input 21 to the timing pulsegenerator 23, but these timing signals, and are approximately out ofphase with each other.

The first timing signal 4: is coupled to a conventional or gate 29 andto a first input terminal 31 of a single pulse forming circuit 33.However, it is to be understood that the principles of the invention areapplicable to any type of logical system and are not limited to binarysystems or to only positive logical systems. The second timing signal iscoupled to a second input terminal 35 of the single pulse formingcircuit 33 and to a conventional and gate 37, all as part of ananticoincident arrangement as will be explained later.

As can be seen in FIG. 1, a mechanical linkage as represented by dashedline 39 coupled a mechanical device 41, such as a conveyor belt forexample, to a slow pulse generator 43 so that the number of slow speedpulses generated 'by the slow pulse generator 43 will be governed by thephysical motion of the mechanical device 41. Thus, where the conveyorbelt, for example, is not moving, no slow speed pulses will begenerated.

The slow speed pulses, when generated, are related by number Withrespect to the speed of the mechanical device or conveyor belt in thiscase and are coupled to a third input terminal 45 of the single pulseforming circuit 33. The output signal of the single pulse formingcircuit is provided at an output terminal 47 and thus provides ananticoincident signal to another input of the and gate 37. The output ofthe anticoincidence and gate 37 depends upon the coincidence andpolarity of the second timing signal and the anticoincident signal andis here shown as precession signal coupled to another input of the orgate 29. I

The or gate 29 provides a counting signal e5 that is fed to a cyclicelectronic circuit such as a conventional binary counter 49. The counter49 may take a multitude of different forms and is not to be limited to abinary counter or to one consisting of conventional single inputflip-flops FF FF as shown. As just mentioned, the flip flops shown areWell known in the art generally referred to as trigger or complementingflip-flops, where any input pulse results in a change in state of theflip-flop.

Each flip-flop stage of the counter 49 includes two output terminals,one of which is coupled to the input of a subsequent series connectedflip-flop stage, except for the last stage. Also, by means of switches 8-8 for example, either output of each flip-flop stage may be selected tobe coupled to one of the multiple inputs to a conventional multipleinput or gate 51. The output of the or gate 51 is coupled to aconventional inverted circuit 53 which together comprise what may becalled a strobe pulse forming circuit 55. Again, the strobe circuit 55need not only be comprised of such elements as the or gate 51 and theinverted 53, but any similarly functioning circuitry may be substitutedtherefor. Thus, it can be seen that each flip-flop stage has an outputcoupled to an input of the or gate 51 and the particular polarity of thevarious inputs to this or gate at any instant of time will depend uponthe state of each particular flip-flop stage FF FF and the selectionmade by the switches S S It should also be noted that the output of eachof the flip-flop stages is coupled in parallel to additional strobepulse forming circuits through similar double-pole switches not hereshown for the sake of clarity. Therefore, it should be understood thatalthough the principles of the invention are applicable to any desirednumber of flip-flop stages and strobe pulse forming circuits, onlyflip-flops FF FP and strobe circuit 55 are illustrated for convenienceof explanation and additional stages and strobe circuits may be includedas, for example, indicated by a dotted strobe circuit 57. The number ofsuch flip-flop stages and strobe circuits actually utilized will begoverned by principles to be explained later.

The output of each strobe pulse forming circuit is what will be called astrobe signal which is coupled to an input of a concidence circuit suchas a coincidence and gate 59. Although only one coincidence circuit isshown, there will be a similar circuit for each strobe pulse formingcircuit utilized in the system. The other input signal to thecoincidence circuit 59 is an information signal that is provided by aconventional binary decoder circuit such as a diode matrix decoder 61that may be coupled through channel amplifiers 63 and 65 to therespective information read heads 13 and 15. It should again beunderstood that although the principles of the invention are applicableto any desired number of information tracks recorded on the cyclicstorage device 11 and corresponding read heads and amplifiers, only twotracks, read heads 13 and 1 5 and amplifiers 63 and 65 are shown forconvenience of explanation and additional tracks, read heads andamplifiers may be included as, for example, indicated by a dottedamplifier 67.

The output signal from the coincidence and gate 59 is an actuationsignal that is provided depending upon the coincidence and polarity ofthe respective strobe signal 4; and the information signal (p arrivingat the inputs of the coincidence and gate 59 and governed by theconventional rules of binary logic, in this example. Each actuationsignal that is provided by each coincidence circuit is coupled to aseparate actuated device such as the electromechanical actuator 69.Thus, if, for example, push-type actuators are to be utilized at variouspoints along a conveyor belt, a separate actuated device would berequired to be disposed at these points to push whatever is so selectedoff of the belt at these predetermined points Before the over-alloperation of the system according to the invention is described, majorcomponent parts will be explained. Thus, FIG. 2 illustrates a timingpulse generator that may be utilized. Here, the inputs 21 of the timingpulse generator 23 couple the timing signal from the amplifier 19 to aconventional flip-flop 101 having opposite polarity signals g5, and raEach of these signals is coupled to a respective one shot multivibrator103 and 105 to provide the timing signals and respectively. Theoperation of the timing pulse generator can best be explained by makingreference to the schematic diagram of waveforms of voltage as a functionof time of FIG. 3. It can be seen that the flip-flop 101 follows theinput sine wave signal and provides square wave shaped signals 1) andthat have substantially the same length as the period of each half-cycleof the sine wave signal S For better useful timing characteristics, thelength of these square wave signals is reduced by the respective oneshot multivibrators 103 and 105 as can be seen in FIG. 3. Thus, it canbe seen that the timing pulse generator 23 produces similarly poled andrelativelyy narrow square wave timing signals 5 and 5 which aresubstantially out of phase with each other.

The schematic block diagram of FIG. 4 illustrates the single pulseforming circuit 33 of FIG. 1. As shown in FIG. 1, this circuit isoperating in an addition mode where each pulse generated by the slowpulse generator 43 is added to the continuing chain of timing pulses ata point approximately equidistant from the preceding and followingtiming pulse so that the counter 49 will have no trouble in recordingits presence. However, this same basic circuit may be used to provide asubtraction function by subtracting one of the 5 timing pulses each timea slow pulse signal p and is produced by the slow pulse generator 43.This is accomplished by making the connections shown in FIG. '1 asdotted lines with respect to the single pulse forming circuit 33 and bybreaking the connections shown by solid lines at the points indicated bythe Xs. This includes coupling the anticoincidence signal through aninverter stage 151 to provide a subtracting signal that along with the 3timing signal 4: is coupled to a subtractor and gate 153 to provide thecounting signal to the counter 49.

The signal pulse forming circuit shown in FIG. 4 comprises a first andsecond and gate input elements 201 and 203. Each of these input elementshas one input 45 coupled to a respective slow pulse signal and 2 whilethe other input of these elements are connected together and to theinput terminal 31. The output terminal of each of the and gates 201 and203 is connectedto separate input terminals 205 and 207 of aconventional first flip-flop 209. The flip-flop 209 has a first outputterminal 211 providing an output signal and a second output terminal 213providing an output signal that is, of course, inversely related to thesignal 5 These output signals are in turn coupled through respectiveinput terminals of third and fourth input elements or and gates 215 and217 to respective input terminals 219 and 221 of a second flip-flop 223when there is present a suitable timing signal from the input terminal35 on the other input terminal of the third and fourth input and gates.

-In a manner similar to the first flip-flop 209, the second flip-flop223 provides output signals em and 5 through fifth and sixth and gates225 and 227 to respective input terminals 229 and 231 of a thirdflip-flop 233 when a suitable timing signal is present at the inputterminal 31. The output terminal 235 of the third flip-flop 233 isconnected to one of the two inputs to an or gate 237 while the otherinput thereof is connected to the second output terminal 213 of thefirst flip-flop 209. Thus, at the or gate 237 input terminals there maybe presented the signals and The or gate 237 is in turn connected to aninverter circuit 239 which is the source of the anticoincident signal 5in the addition mode of operation previously described.

The operation of the single pulse forming circuit and theanticoincidence circuitry relating thereto may be best understood byreferring to the waveforms of voltage as a function of time illustratedin FIG. 5. This diagram describes the inter-relationship between thevarious elements of the circuit functioning in the addition mode.Considering that all higher level voltages are true and all lower levelvoltages are false, it can be seen that the two timing signals 5 andcontrol the various flip-flops in the circuit. Thus, whenever the slowpulse generator 43 produces a true slow speed signal (because ofmovement of a conveyor belt, for example) that is coincident in timewith a true qb timing signal at the first and gate 201, the firstflip-flop 209 will be set to produce a true first output signal at thefirst output terminal 211.

At the same instant, of course, a false second output signal ispresented at the second output terminal 213. The resetting of theseflip-flops and others later to be described is accomplished in aconventional manner easily understood from the waveform diagrams and,therefore will not be described in detail.

In a manner similar to the setting of the first flip-flop 209, thesecond flip-flop 223 is set when there is a coincidence at the third andgate 215 of a true timing signal and the true first output signal gbThere is thus provided a true third output signal coupled to the fifthan gate 225 and a false fourth output signal coupled to the sixth andgate 227. Again, with the coincidence at the fifth and? gate 225 of thetrue third output signal and a true timing signal, the third flipfiop233 will be set so that a true fifth output signal 5 is produced andcoupled to the or gate 237. This or gate 237 is the non-exclusive typeand functions to provide at its output a false signal whenever both ofits inputs are false, but a true signal if either or both of its inputsare true. The inverter 239 will, of course, invert a false input to atrue output and vice versa. Thus, at the output terminal 47 of thesingle pulse forming circuit 33 a true anticoincidence signal willappear and be coupled to the and gate 37 only when the second outputsignal (p and the fifth output signal are both false at the same time.It can thus be recognized that the function of the single pulse formingcircuit 33 as just described is to provide a true anticoincidence signalwhenever a slow speed signal 5 is produced, which anticoincidence signalalways commences at the time of the next occurring timing signal andalways terminates at the time of the next subsequent timing signal, nomatter the duration of the slow speed signal from the slow pulsegenerator 43.

FIG. 5 also describes the inter-relationships of the anticoincidencesignal 5 the precession signal and the counting signal Thus, only whenthere is a coincidence of a true timing signal and a trueanticoincidence signal n at the inputs to the anticoincidence and gate37 will the precession signal 45 be true. Therefore, it should be clearthat the function of the anticoincidence circuit is to allow theinsertion of a pulse into the chain of #1 timing signals (whenever aslow speed signal is generated) only at the time a true timing signal ispresent. This guarantees that the added pulses are insertedsubstantially equidistant in time between 5 timing signals so that therewill be no possibility that the counter 49 will miss a count. Forexample, note in FIG. 5 that true counting signals are present wheneverthere is a true qt timing signal and whenever there is a true countingsignal 5 This is the case because in the circuit of FIG 1 the timingsignal and the counting signal are coupled to the input of the or gate29.

With regard to the subtraction mode of the system, it should be easilyunderstood that by reversing the and timing signals to the inputterminals 31 and 35 of the single pulse forming circuit 33 a true pulsewill occur only at the time a true timing signal is present (after theoccurrence of as low speed signal 5 and false at all other times. Thissignal will be inverted by the inverter 151 to provide a subtractionsignal that is coupled along with the timing signal to the inputs of thesubtraction and gate 153. Now, the subtraction signal will be true atall times except after the occurrence of a slow speed signal (p and thusthe and gate 153 will pass timing signals to the counter 49 except whenthe subtraction signal is false. This, if it occurs at all, must occurat the time is present at the and gate 153 because of the timing of thesingle pulse forming circuit as described above with reference tot herelated dated connection portion of FIG. 1, i.e., reversing theconnections to the Q51, signals.

As can be seen from FIG. 1, the counting signal is coupled to the firstflip-flop FF of the binary counter 49. This first stage is coupled inturn to the second flip-flop F1 and that to the next and so On. Eachflip-flop stage has two output terminals, one of which may be selectedby the switches 8 -5 to be coupled to the multiple input of the or gate51. This selection is governed by a particular predetermined count thatis desired to be forwarded to the inverter 53 to form the strobe signalIn this example, there are eight flip-fiop stages and thus the counter49 wil count 256 456 pulses before it recycles. By proper selection ofthe switch positions, any one pulse of the 256 pulses per cycle can beselected to be the strobe signal by each strobe pulse forming circuit.This can best be explained by stating first that the strobe pulseforming circuits will provide a true strobe signal only when all of theinputs to the or gate 51 are false; if any of these inputs are true, thestrobe signal will be false. Thus, by using binary logic, it can be seenthat this condition of all false outputs of the counter 49 can beselected by the switches 8 -8 For example, the first flip-flop stage FF1 will represent the units digit and the second flip-flop FF willrepresent the 2 digit. The third flip-flop will be 4; the fourth will be8; the fifth, 16; the sixth, 32; the seventh, 64; and the last, 128.Thus, the binary selection as shown by the position of the switches inFIG. 1 is 1 plus 4, plus 16, plus 64 or a total of 85. In this case, atthe time that the th true counting signal pulse appears at the counter49 after its last reset, all the inputs of the or gate 51 would be lowand a true strobe signal pulse 5 will be coupled to the coincidence andgate 59. Of course, each strobe pulse forming circuit has its own set ofselection switches so that a different count may be selected for it.

The cyclic storage device 11, on the other hand, must through itsdecoder circuit 61 be able to provide a true information signal pulse atany of the counts that the counter can register per cycle of itsoperation, In this case, the decoder should be able to provide a truepulse to coincide with a true 4, pulse a the inputs to the coincidenceand gate 59. However, the main consideration above all is that both thecyclic storage device and the cyclic electronic circuit recycle in thesame amount of time so that in the absence of precession true pulses andtrue 4),; pulses will remain stationary in time with respect to eachother. This can be clearly seen in FIG. 6 before the occurrence of thetrue 5 signal pulse. In the case where, as shown, the cyclic memory is adrum type memory with a timing track, there must be as many timingpulses read in any revolution of the drum as the total number of pulsesthe counter can count before it recycles. In other words, the countermust recycle once for each revolution of the drum.

The cyclic memory drum 11 will accordingly have as many memory tracks aswill be required to produce (after decoding) an information signal thatwill match any of the possible timing positions possible for the strobesignal at each coincidence circuit taking into consideration that thebinary decoder provides 2 possible outputs for N inputs. Thus, wherethere are eight actuation devices in a system, then only three trackswill be needed and not eight as is required by most prior art systems.

The precession that occurs between the strobe signal 457 and theinformation signal in order to obtain a coincidence of true pulses ofthese signals at any particular coincident circuit, can best beexplained by again making reference to FIG. 6. Here, it can be seen thatthe information signal pulses are always equally spaced in time as isthe case with the strobe signal pulses #7 before the occurrence of aslow speed signal pulse However, when each pulse does appear, thedistance or time between consecutive strobe pulses lessens until the andpulses coincide in time When this happens at a particular coincident angate 59, at true actuation signal pulse will be coupled to an associatedactuator 69. Thus, in the case of a conveyor belt for example, when thebelt has moved a predetermined distance and the slow pulse generator 43produced a certain number of slow speed signal pulses a package may bepushed from its position on the belt onto another conveyor or onto adock area for transportation to its ultimate destination.

The more precise the positioning of each actuator along the line oftravel of the belt is desired, the higher the total number of timingsignal pulses 5 must be generated and counted per cycle of operation ofthe counter and, of course, the memory. In other words, the total numberof timing pulses per cycle is governed by the desired length of eachincrement of distance along the conveyor. For example, where theconveyor is 256 feet in length and there are 256 pulses counted by thecounter each cycle of its operation, then the increment of length inwhich any actuator can be placed is 1 foot. Thus, the closest that anytwo actuators can be placed is 1 foot.

Thus, there has been described an improved synchronized control systemthat synchronizes electronic circuitry with slow moving equipment suchas, for example, conveyor belts and the like. It has been shown thatthis system is simpler, cheaper and smaller than systems heretoforeavailable to produce the same result and does not use a slow speedstorage device.

Although specific embodiments of the invention have been described indetail, other organizations of the embodiments shown may be made withinthe spirit and scope of the invention.

Accordingly, it is intended that the foregoing disclosure and drawingsshall be considered only as illustrations of the principles of thisinvention and are not to be construed in a limiting sense.

What is claimed is:

1. A synchronized control system to control electromechanical actuatorsassociated with a relatively slow speed mechanical device, comprising:

relatively high speed cyclic storage means having a cyclic cycle ofoperation for providing storage information signals in accordance withpredetermined information stored therein;

relatively high speed cyclic electronic circuit means for generatingstrobe pulses for any of its states corresponding to any desired pointsin the storage cycle of said cyclic storage means;

relatively slow speed pulse generator means coupled to said slow speedmechanical device for generating slow speed pulses related to themovement of said mechanical device;

timing pulse circuitry means coupled to said slow speed pulse generatormeans and responsive to said slow speed pulses, to said cyclic storagemeans and to said cyclic electronic circuit means for providing asynchronous timing relationship therebetween, for providing timingpulses to said cyclic electronic circuit means and for causing aprecession of said strobe pulses with respect to said storage cycle ofsaid cyclic storage means by controlling the number of said timingpulses coupled to said cyclic electronic circuit means in accordancewith said slow speed pulses; and

actuation means coupled to said cyclic electronic circuit means and tosaid cyclic storage means and responsive to the relationship of saidstorage information signals and said strobe pulses for providingactuation signals to be coupled to said electromechanical actuators.

2. A synchronized control system according to claim 1, wherein saidcyclic storage means includes a plurality of stored information segmentsrecorded in a cyclic memory device for providing said informationsignals.

3. A synchronized system according to claim 1, wherein said timing pulsecircuitry means includes timing pulse generator means for generatingsaid timing pulses.

4. A synchronized control system according to claim 3, wherein saidtiming pulse circuitry includes additive single pulse forming circuitmeans for adding timing pulses to said timing pulses generated by saidtiming pulse generating means in direct relationship to the number ofsaid slow speed pulses produced by said slow speed generator means. i

5. A synchronized control system according to claim 3, where-in saidtiming pulse circuitry includes subtractive single pulse forming circuitmeans for subtracting from said timing pulses coupled to said cyclicelectronic circuit means in direct relationship to the number of saidslow speed pulses produced by said slow speed generator means.

6. A synchronized control system according to claim 1, wherein saidtiming pulse circuitry means includes a timing pulse generator producinga continuous train of said timing pulses and a second continuous trainof timing pulses having a phase relationship to said mentioned timingpulses of approximately 3. single pulse forming circuit having firstinput terminals coupled to said slow pulse generator means and secondinput terminals coupled to said timing pulse generator and responsive tosaid trains of timing pulses and output terminals whereat there isprovided an anticoincident pulse signal; an and gate having a firstinput coupled to said timing pulse generator and responsive to saidsecond train of timing pulses and a second input coupled to said timingpulse generator and responsive to said first mentioned train of timingpulses and an output whereat there is provided a precession pulse signalwhen there is a coincidence at said first and second inputs of said andgate of a pulse from said second train of timing pulses and a pulse fromsaid anticoincident pulse signal; and an or gate having a first inputcoupled to said timing pulse generator and responsive to said firstmentioned train of timing pulses and a second input coupled to saidoutput of said and gate and an output coupled to said cyclic electroniccircuit means to supply counting signal pulses for each of said timingpulses and the precession signal pulses.

7. A synchronized control system according to claim 1, wherein saidcyclic electronic circuit means includes a binary counter comprising aplurality of binary stages coupled in series and a plurality of strobepulse forming circuits, each coupled in a predetermined manner to adiiierent one of said binary stages.

8. A synchronized control system according to claim 1, wherein saidactuation means includes a plurality of electromechanical actuators anda coincident circuit for each of said actuators coupled to correspondingones of said actuators, said coincident circuits having a first inputterminal coupled to said cyclic electronic circuit means and responsiveto said strobe pulses and a second input terminal coupled to said cyclicstorage means and responsive to said storage information signals andproviding actuation signals to corresponding ones of said actuators whenthere is a timing and polarity coincidence between said strobe pulsesand said stoarage information signals at said input terminals thereof.

9. A synchronized control system according to claim 8, wherein saidcoincident circuit is an and gate.

10. A synchronized control system according to claim 1, wherein saidcyclic storage means includes a drum memory of a binary decoder thereto.

References Cited UNITED STATES PATENTS ROBERT K. SCHAEFER, PrimaryExaminer. T. B. JOIKE, Assistant Examiner.

US. Cl. X.R. 214-11

